Paul graduated from The University of Manchester Institute of Science and Technology in 1991 and 1992 with a BEng in Electronic Engineering and an MSc in VLSI Systems Engineering. He worked as a Research Assistant at the University for two years in the Computation department, researching Object Oriented Hardware/Software co-design on ESPRIT funded initiatives - Attempting to show how systems described at a higher level of abstraction could be committed to hardware or software and designed in VHDL or C as appropriate.
Paul joined Roke Manor Research ® in 1994 as a Senior Engineer/Project Manager and worked on various projects including ATM switches, ASIC and FPGA design, Systems Architecture design and Software implementation. He left in 1999 to work as an independent consultant and worked on various designs including a dual channel Ethernet Packet Analyser, ATM Analyser and a systems design for a next generation Terabit IP router.
He joined Semtech Ltd ® in 2001 and worked on several designs specialising in synchronisation, packet technologies and data network systems. Principle among these designs was the ToPSync ® ASIC, the world's first timing recovery chip for packet networks, for which he was the principle architect, designer and Programme Manager. During his time at Semtech Paul studied for an MBA part time at Southampton University and graduated in 2007.